1. Field of the Invention
The present invention relates to a semiconductor memory device such as a memory card, host device and semiconductor memory system, in particular, to a technique for recovering a writing error occurring in a nonvolatile memory within the semiconductor memory device.
2. Discussion of the Related Art
Conventionally, a semiconductor memory device such as an SD (Secure Digital) card as a card-type recording medium which has a flash memory therein is very small and thin and due to its handiness, is widely used for recording data such as images in a digital camera, portable equipment and so on.
The flash memory contained in the semiconductor memory device is a nonvolatile memory which can erase and rewrite data in units of block of a uniform size. To address a demand for an increase in capacity in recent years, the flash memory capable of storing data of two bits or more in one cell has been commercialized.
Referring to FIGS. 1A, 1B and 2, relationship between the number of electrons accumulated in a floating gate of an MCL (multi-level cell) flash memory (hereinafter referred to as a multi-level flash memory) which expresses 2-bit information per cell and a threshold voltage (Vth).
FIG. 1A shows a configuration of one cell of a flash memory. A flash memory 10 is configured by forming an N-channel source and drain electrodes 12, 13 on a P-channel substrate 11 and laminating a tunnel oxide film 14, a floating gate 15, an insulating oxide film 16 and a control gate 17 between the source electrode 12 and drain electrode 13. Thus, as distinct from a volatile dynamic random access memory (DRAM), the flash memory has the floating gate 15 as an area for holding an electrical charge within a transistor. A voltage threshold during current flows changes depending on a state of the electrical charges accumulated in the floating gate 15. FIG. 1A shows an initial state before data writing where electrical charges are not accumulated and FIG. 1B shows a state where electrical charges are accumulated and data is written.
FIG. 2 shows an example of relationship between the number of electrons accumulated in the floating gate of a multi-level flash memory and a threshold voltage (Vth). In a case of a binary flash memory, a voltage during the current flows changes depending on the presence or absence of electrons in the floating gate. However, in a case of a four-level flash memory expressing 2-bit information per cell, four threshold voltages during the current flow exist depending on the amount of electrical charges. As shown in FIG. 2, in the four-level flash memory, an electron accumulating state in the floating gate is managed in four states according to its threshold voltage (Vth). An electric potential in an erasure state is the lowest and this state is defined as (1, 1). As electrons are accumulated, the threshold voltage discretely rises and these states are defined as (1, 0), (0, 0) and (0, 1). Since the electrical potential rises in proportion to the number of accumulated electrons, data of two bits can be recorded in one memory cell by controlling the electrical potential so as to fall below a predetermined threshold value.
FIG. 3 is a schematic diagram of one physical block of the four-level flash memory. The physical block shown in FIG. 3 is formed of 2K (K is a natural number) pages. Writing processing is performed from a page number 0 in ascending order. Here, it is assumed that a page with a page number m (0=m<K) and a page with a page number (K+m) share one memory cell (hereinafter referred to as cell sharing relationship). In pages having the cell sharing relationship, a page to be written first is referred to as a first page and a page to be written next is referred to as a second page. In other words, writing to the page number m (writing to the first page) and writing to the page number (K+m) (writing to the second page) mean that electrons are charged to a same cell. Describing referring to FIG. 2, it is controlled so that the electrical potential only rises up to a half at a maximum in writing to the first page and rises from the half to the maximum in writing to the next second page.
FIG. 4 shows shift of the state of the flash memory cell. As shown in FIG. 4, a state of one memory cell of a physical block of the flash memory shifts as follows.
(a) The memory cell state is (1, 1) after data erasure.
(b) The memory cell state is (1, 1) or (1, 0) after writing to the first page.
(c) The memory cell state is (1, 1), (1, 0), (0, 0) or (0, 1) after writing to the second page.
As described above, in the multi-level flash memory, multi-level recording of providing a plurality of states of the threshold voltage Vth and controlling an amount of accumulated electrons is performed, thereby realizing an increase in capacity.
The above-mentioned cases (b), (c) will be described in more detail. In the case (b), a state after 1 is written to a corresponding logical page is (1, 1). A state after 0 is written is (1, 0). In the case (c), shift is limited depending on the state of the case (b). That is, in shift from the state (1, 1) in (b), the state (1, 1) is maintained when 1 is written and the state (1, 1) shifts to the state (0, 1) when 0 is written. Meanwhile, in shift from the state (1, 0) in (b), the state (1, 0) is maintained when 1 is written and the state (1, 1) shifts to the state (0, 0) when 0 is written. Thus, in a same physical page, a value in the first page is reflected on a second bit and the value in the second page to be written next is reflected on a first bit.
The flash memory uses a tunnel oxide film 14 having an insulating function to hold the electrical charges accumulated in the floating gate 15. In writing and erasure, electrons pass through the oxide film and thus, an oxide film becomes to deteriorate. When writing is repeated, the oxide film is damaged and cannot act for insulation. For this reason, the flash memory has the feature that the number of times of writing is limited.
Next, an occurrence of the write error will be described. In the case of the four-level flash memory, the memory cell is shared by two logical pages of the first page and second page. Writing to the pages 0 to (K−1) in FIG. 3 is writing to the first page. In this case, a write error is due to that Vth does not rise from the state of (1, 1) to the state of (1, 0). Writing to pages K to (2K−1) in FIG. 3 is writing to the second page and a state of Vth becomes (1, 1), (1, 0), (0, 0), (0, 1). In this case, the write error is due to that:
(Error 1) Vth does not rise from (1, 0) to (0, 0); and
(Error 2) Vth does not from (1, 0) to (0, 1).
Vth (1, 0) is adjacent to Vth (0, 0) in the case of the error 1, while two states are interposed between Vth (1, 1) and Vth (0, 1) in the case of the error 2. Especially Vth (1, 0) is a value after writing to the first page and in a case where Vth only rises to (1, 0) after writing to the second page, the second page has a write error, further causing corruption of data in the first page.
Next, the possibility that the write error destroys another file will be described in more detail. A left side in FIG. 5 shows a logical block in a logical address space and corresponds to the physical block in a physical address space of a flash memory in a right side in FIG. 5. A file 1 has been already written to the physical block and a file 2 is added later. It is assumed that the file 1 has been already recorded from the page 0 to the page (K−2) in the physical address space and the file 2 is added from the page (K−1) to the page (2K−1). In this example, for simplification of description, the gages are used in ascending order. During writing of the file 2, for example, as shown in FIG. 5, data written to the page 0 can be destroyed due to a write error occurred during writing to the page k or sudden power disconnection. In other words, when the data in the page 0 is destroyed, the file 1 may be also destroyed by writing of the file 2.
To solve this problem, in Japanese Unexamined Patent Publication No. 2006-318366, a memory controller for controlling a flash memory is provided with a buffer memory and data in a first page is stored in the buffer memory until writing to a second page is completed, and when a write error occurs due to writing to the second page, the data in the buffer memory is loaded and the data in the first page is also written to the flash memory.